The present invention generally relates to semiconductor devices and more particularly to a capacitor and manufacturing method thereof as well as a substrate having a capacitor.
With sharp increase of clock frequency in recent advanced semiconductor devices, supply of a stable electric power to semiconductor chip is becoming a paramount problem. In order to deal with this problem, there is a proposal to provide a capacitor on a substrate on which the semiconductor chip is mounted.
FIG. 20 shows a conventional semiconductor device 10.
Referring to FIG. 20, the semiconductor device 10 includes a substrate 11 mounted with a semiconductor chip 12, wherein the substrate 11 includes a substrate body 13 and a decoupling capacitor 14. The decoupling capacitor 14 is provided inside the substrate body 13. The decoupling capacitor 14 includes a dielectric film 16 formed on a silicon substrate 15, and a conductive film 17 is provided further on the dielectric film 16. Reference should be made to Japanese Laid-Open Patent Publication 2001-274034.
Here, it should be noted that the capacitor 14 is constructed on the silicon substrate 15 used as a support body, and thus, it is necessary to scribe the silicon wafer carrying the films 16 and 17 thereon at the time of the dicing process, while such a dicing process takes time and the efficiency of manufacturing a semiconductor device is decreased. Further, there is a need of complex process such as dry etching, wet etching or laser processing at the time of forming a through hole in the silicon substrate 15. Thus, such a complex process causes further degradation in the efficiency of manufacturing a semiconductor device.
Further, associated with the use of the silicon substrate 15 for the support of the capacitor, there arises a problem that the capacitor 14, and hence the substrate 11, inevitably has a considerable thickness.
Further, because of the fact that the capacitor is disposed offset in the construction of FIG. 20 from the surface of the substrate 11, on which the semiconductor chip 12 is mounted, there arises a problem in that the length of the conductor path connecting the semiconductor chip 12 and the capacitor 14 is increased. Associated with this, there occurs the problem of increase of parasitic inductance in the foregoing conductor path, and it becomes difficult to achieve the desired stabilization of the supply voltage to the semiconductor chip 12 because of the increased parasitic inductance in the case the operational frequency of the semiconductor chip 12 has been increased.